// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.9.0.99.2
// Netlist written on Mon May 08 14:05:59 2017
//
// Verilog Description of module pwmpulse
//

module pwmpulse (clk, rst_n, pwm) /* synthesis syn_module_defined=1 */ ;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(23[8:16])
    input clk;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(40[9:12])
    input rst_n;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(40[13:18])
    output pwm;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(45[9:12])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(40[9:12])
    
    wire GND_net, VCC_net, rst_n_c, pwm_c;
    wire [3:0]count;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(56[13:18])
    
    wire n70, n1, n132, n22, n23, n24;
    
    VHI i2 (.Z(VCC_net));
    FD1S3IX count_22__i3 (.D(n22), .CK(clk_c), .CD(n70), .Q(count[3]));   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(67[11:18])
    defparam count_22__i3.GSR = "ENABLED";
    VLO i93 (.Z(GND_net));
    OB pwm_pad (.I(pwm_c), .O(pwm));   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(45[9:12])
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    TSALL TSALL_INST (.TSALL(GND_net));
    FD1S3IX count_22__i0 (.D(n1), .CK(clk_c), .CD(n70), .Q(count[0]));   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(67[11:18])
    defparam count_22__i0.GSR = "ENABLED";
    LUT4 i84_2_lut (.A(count[1]), .B(count[3]), .Z(n132)) /* synthesis lut_function=(A (B)) */ ;
    defparam i84_2_lut.init = 16'h8888;
    LUT4 i55_2_lut (.A(count[1]), .B(count[0]), .Z(n24)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(67[11:18])
    defparam i55_2_lut.init = 16'h6666;
    LUT4 i62_2_lut_3_lut (.A(count[1]), .B(count[0]), .C(count[2]), .Z(n23)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(67[11:18])
    defparam i62_2_lut_3_lut.init = 16'h7878;
    LUT4 i69_3_lut_4_lut (.A(count[1]), .B(count[0]), .C(count[2]), .D(count[3]), 
         .Z(n22)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(67[11:18])
    defparam i69_3_lut_4_lut.init = 16'h7f80;
    IB clk_pad (.I(clk), .O(clk_c));   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(40[9:12])
    LUT4 i92_4_lut (.A(count[0]), .B(count[1]), .C(count[2]), .D(count[3]), 
         .Z(pwm_c)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
    defparam i92_4_lut.init = 16'h0001;
    LUT4 i24_1_lut (.A(count[0]), .Z(n1)) /* synthesis lut_function=(!(A)) */ ;   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(64[11:25])
    defparam i24_1_lut.init = 16'h5555;
    GSR GSR_INST (.GSR(VCC_net));
    LUT4 i89_4_lut (.A(n132), .B(rst_n_c), .C(count[0]), .D(count[2]), 
         .Z(n70)) /* synthesis lut_function=(!(A (B ((D)+!C))+!A (B))) */ ;
    defparam i89_4_lut.init = 16'h33b3;
    FD1S3IX count_22__i2 (.D(n23), .CK(clk_c), .CD(n70), .Q(count[2]));   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(67[11:18])
    defparam count_22__i2.GSR = "ENABLED";
    FD1S3IX count_22__i1 (.D(n24), .CK(clk_c), .CD(n70), .Q(count[1]));   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(67[11:18])
    defparam count_22__i1.GSR = "ENABLED";
    IB rst_n_pad (.I(rst_n), .O(rst_n_c));   // e:/git/oschina/step_mxo2/labs/src/pwmpulse.v(40[13:18])
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

